The present invention relates to systems for testing integrated circuit chips (IC-chips). More particularly, the present invention relates to the structure of modules in the above systems which hold the IC-chips in sockets on circuit boards while the IC-chips are tested.
In the prior art, one system for testing IC-chips is disclosed in U.S. Pat. No. 6,363,510 by J. Rhodes et al. which is entitled “AN ELECTRONIC SYSTEM FOR TESTING CHIPS HAVING A SELECTABLE NUMBER OF PATTERN GENERATORS THAT CONCURRENTLY BROADCAST DIFFERENT BIT STREAMS TO SELECTABLE SETS OF CHIP DRIVER CIRCUITS”. A block diagram of the above prior art system is shown in FIG. 1 of the '510 patent, and that figure is reproduced herein as FIG. 1.
Inspection of FIG. 1 shows that the chip testing system of patent '510 includes a plurality of chip holding modules, each of which is identified by reference numeral 10. Each chip holding module 10 is comprised of one printed circuit board 10b on which several sockets 10c are soldered, and each socket is structured to hold one IC-chip 10a that is to be tested.
The chip testing system of FIG. 1 also includes a separate chip driver module 11 for each chip holding module 10. In operation, the chip driver modules 11 send test signals to the IC-chips 10a on the chip holding modules 10, and the chip driver modules 11 also receive output signals from the IC-chips 10a as a response. All of these signals travel between the IC-chips 10a and the chip driver modules 11 via conductors 10 on the chip holding modules, connectors 10d on the chip holding modules, matching connectors (not shown) on the chip driver modules, and cables (shown as solid lines) which extend from one connector to another.
In order to be able to test many different types of IC-chips 10a with the system of FIG. 1, the test signals which are sent to the IC-chips need to have selectable voltage levels. For example, some types of IC-chips operate with test signals of “0” and “2.0” volts, whereas other types of IC-chips operate with test signals of “0” and “1.5” volts. Test signals with such different voltage levels are generated by including in each chip driver module 11, one signal translator circuit for each test signal which that chip driver module sends to an IC-chip 10a. 
Now, a major drawback with the above chip testing system of patent '510 is that the total number of signal translators, connectors, and cables to those connectors which are required to generate and send the test signals is very large. This is evident from the following numerical example.
In a typical chip testing system which meets the industry standard called IEEE1149.1, each IC-chip 10a is tested by sending twenty test signals in parallel to the IC-chip and by receiving one signal in response. The twenty test signals that are sent to each IC-chip 10a are called TCK, TDI, TMS, HFCLK and vectors V1 thru V16. The one signal that is received from each IC-chip as a response is called TDO. Also, the number of sockets 10c in each chip holding module 10 is typically at least sixteen, and the number of chip holding modules 10 in one chip testing system is typically at least ten. FIG. 2 of the '510 patent shows a system with eleven chip holding modules.
Multiplying twenty times sixteen times ten yields a total of three thousand two hundred. Thus, at least that many signals need to be translated and carried by the connectors, with their cables, in the FIG. 1 system of patent '510. But all of those components add cost to the system and thereby make the system less competitive in the market place.
To address the above problem, each chip holding module 10 and each driver module 11 in the FIG. 1 system of patent '510 can be modified as shown herein in FIG. 1A. There, the modified chip holding module is indicated by reference numeral 10′, and the modified chip driver module is indicated by reference number 11′.
In the modified chip driver module 11′, the voltage levels of the signals TCK, TDI, TMS, HFCLK, and V1–V16 are translated from zero and VH1 to zero and VH2 by a single set of signal translator circuits 11x. The voltage level VH2 is determined by the magnitude of an analog V+ input to each signal translator circuit 11x. One such signal translator in the prior art, which is actually used in the chip testing system of patent '510, is the Edge 692 Dual Pin Electronics Driver from Semtech Corporation of California.
All of the above voltage translated signals in FIG. 1A are carried by a single cable 10x from a single connector 11y on the modified driver module 11′ to a single connector 10y on the modified chip holding module 10′. A single bus 10z on the modified chip holding module 10′ carries the voltage translated signals from the connector 10y to all of the IC-chips 10a. The TDO signals from the IC-chips 10a ar sent back to the modified driver module 11′ over another cable with a connector on each end (not shown).
However, with the single bus structure of FIG. 1A, several other technical drawbacks arise. For example, suppose that one of the IC-chips 10a has a defect which shorts a particular input on the chip to ground. Then, if the shorted input receives a test signal from the bus 10z, the bussed test signal will be forced low on all of the IC-chips 10a which are held by the sockets 10c on the chip holding module 10′. Thus, all of the IC-chips 10a will fail their test even though only one IC-chip has a defect.
Accordingly, a primary object of the present invention is to provide a novel architecture for a module that holds IC-chips in a chip testing system which overcomes the above problems.